This application is based upon and claims priority from prior French Patent Application No. 98-16217, filed Dec. 22, 1998, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to computer systems, and more specifically to a method for computed-assisted design of a processor core.
2. Description of Related Art
A processor core (or microprocessor core) is a set of resources that performs vital processor functions, and chiefly includes an instruction decoder, control circuits to manage an instruction register, an arithmetic and logic unit, a program counter containing the current address of the program, and the like. In general, a certain number of optional peripheral resources for the processor are proposed to make it possible to meet the specific needs of users. For example, possible peripheral resources include a digital-to-analog converter, a counter, and the like.
Furthermore, from one application to another, these resources may be configured at different physical addresses in the address space of the processor (which is defined by the width of the address and data busses) and with different access modes depending on the needs of the users. The processor core must know the physical addresses of the different peripheral resources of the processor in the address space of the processor, as well as their mode of access (typically the 8-bit multiplex mode or the 16-bit demultiplex mode), and this must be known as soon as the resetting signal ends. For this purpose, configuration registers are normally provided in order to contain the physical addresses of these resources and their corresponding mode of access. The programming of these configuration registers is obtained by wiring each of the bits of these registers either to 1 (by connecting the bit to VDD) or to 0 (by connecting the bit to ground).
FIGS. 1 and 2 show conventional processor cores. In the processor of FIG. 1, the configuration registers such as register R1e are physically outside the core. In this case, it is necessary to raise each bit b1 to bn of the registers up to the corresponding decoding block DEC in the core. Thus, an input pin is planned for each bit of the configuration registers in the layout diagram of the core. In the example, there are pins s1 to sn. In the processor of FIG. 2, the configuration registers such as register R1i are provided within the core itself. In both cases, this programming is permanent and definitive. The corresponding decoding block therefore cannot be tested in the core except with the definitive values taken by the bits of the configuration registers. This means that it is impossible to provide for complete coverage of the testing of the block.
Furthermore, with the configuration method shown in FIG. 1, it may be necessary to provide many input pins in the layout diagram of the core, depending on the number of resources made available to the choice of the user (i.e., the number of bits needed to encode all the physical addresses and the corresponding access modes). This leads to an increase in the dimensions of the core of the processor. As a tradeoff for providing this number of input pins, the positioning of these registers outside the core makes it possible to have only one core meeting the needs of all the applications (i.e., all the possible core and resource combinations).
With the configuration method shown in FIG. 2, there are no input pins to be planned but the core is then dedicated to one type of application. To each different application, there corresponds a new core. It is furthermore necessary to plan for a different core to make the corresponding emulator. Indeed, it is necessary in the emulator to be able to configure any address or any resource access mode. It is therefore necessary to plan input pins for the configuration bits as in FIG. 1 and external registers to drive the configuration bits.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide testability of the decoding block in a processor core while ensuring the irreversibility of the programming of the configuration registers.
Another object of the present invention is to provide a complete coverage of the testing of the decoding block of a processor core, with all of the possible values in the configuration registers.
Yet another object of the present invention is to provide a method for designing a processor core that enables the maintaining of a single processor core that is the same for the entire family, including the emulator.
One embodiment of the present invention provides a method for designing a processor core. According to the method, configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. In a preferred embodiment, both the cells configured at one and at zero have the same abstract defining their space requirements and input and output pins.
Another embodiment of the present invention provides a method for designing and programming a processor core of the type having configuration registers. According to the method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero. The processor core is programmed by instantiating the non-programmed core, instantiating a programming block having a cell configured at either one or zero for each bit of the configuration registers, and superimposing each of the configured cells of the programming clock on the location of a corresponding vacant cell in the non-programmed core. In one preferred method, each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.